By Topic

A single-chip FPGA implementation of the data encryption standard (DES) algorithm

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
K. Wong ; Inf. Security Res. Centre, Queensland Univ. of Technol., Brisbane, Qld., Australia ; M. Wark ; E. Dawson

This paper describes a single-chip implementation of the data encryption standard (DES) using Xilinx XC4000 series field programmable gate array technology under the XACTstep design flow integration system. The implementation details for key scheduling, S-boxes, permutations and the round-function are described. The design process included schematic design, functional and timing simulation and design verification. The final design used 224 combinational logic blocks (CLBs) and 54 input/output blocks (IOBs) and has an encryption speed of 26.7 Mbps

Published in:

Global Telecommunications Conference, 1998. GLOBECOM 1998. The Bridge to Global Integration. IEEE  (Volume:2 )

Date of Conference:

1998