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Fabrication of wafer level chip scale packaging for optoelectronic devices

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5 Author(s)
Jim, K.L. ; Dept. of Eng. Sci., Oxford Univ., UK ; Faulkner, G.E. ; O'Brien, D.C. ; Edwards, D.J.
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A novel, simple processing and wafer level packaging method for a 4×4 Resonant Cavity LEDs chip with individual array is under development. Palladium/Gold (Pd/Au) alloys are used as p-type contacts and as rewiring metallization for optoelectronic devices to improve the fabrication process. By use of these alloys we have found a reduction of a factor of 10 in the resistance compared to Titanium/Gold (Ti/Au), due to the formation of a conducting oxide at the interface between the metal and semiconductor. On the packaging side, electroplated solder deposition was used to fabricate eutectic solderbump arrays on the chip. For the Under Bump Metallurgies (UBM), a thin layer (100 nm) of Ti and a layer (200 nm) of Cu was sputtered on the wafer. A 10 μm thick copper stud is platted on top of the UBM to be used as a stem for the solder

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Electronic Components and Technology Conference, 1999. 1999 Proceedings. 49th

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