Wafer scale packaging based on underfill applied at the wafer level for low-cost flip chip processing

The key to low cost and high profit margins in flip chip assembly is high process throughput. While flip chip technology has been widely publicized over the last several years, little attention has been paid to process throughput while the majority of work has concentrated on interconnect technologies. The purpose of this project is to develop process technologies and material systems which could make the flip chip assembly process transparent to SMT and packaging and assembly lines by eliminating flip chip flux application, underfill application, and underfill cure processes by using reflowable encapsulants applied to bumped flip chip wafers. This paper presents an evaluation of several methods of material deposition at the wafer level over bump geometries and discusses critical factors and challenges involved therein. Some of the factors include polymer film thickness and uniformity, including edge effects, shadowing, and non-conformal coatings over the bumped regions of the wafer. This paper also discusses the process technology, challenges, and preliminary yield analysis associated with the assembly of pre-underfilled chips directly to low-cost substrates. Of particular interest is how a placement machine handles coated die. In general, the quality of the material coating is dependent on drying method, application method, and the material's theology. Multiple coats, when necessary, serve to provide beneficial leveling of the material. A commercial placement machine is capable of imaging bumps on a coated die and placing it, given the correct set of lighting conditions and transforms. Increasing placement pressure aids in reflow