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Single-probe traversal optimization for testing of MCM substrate interconnections

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3 Author(s)
R. Pendurkar ; Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA ; C. Tovey ; A. Chatterjee

In this paper, we investigate the problem of electrical testing of multichip modules (MCM's) substrate interconnections prior to chip assembly. Recently, single-probe test techniques for MCM substrate interconnections have been proposed that provide fault coverage comparable to double-probe test techniques. This work has two objectives. First, we assess the advantage of single-probe test techniques over double-probe techniques where overall test time is concerned. Second, we develop efficient heuristics to optimize the total distance traveled by a single test probe on an MCM substrate and thereby reduce the substrate testing time. We provide tight bounds on both single- and double-probe testing times. For substrates with two to three terminal pads in each of n nets, the expected travel time for a single probe is shorter by a factor of order n¼. Experiments on benchmark MCM netlists with real probe traversal speeds confirm that single-probe testing has an increasing advantage over double-probe testing, as the number of nets increases. For an MCM substrate of 800 nets, the projected test time is faster by a factor of 2.5. A practical algorithm for finding efficient traversal routes is presented. It is based on heuristic procedures of tour construction and local improvement for solving a variation of the traveling salesman problem. Experiments show that up to 40% reduction in probe traversal time can be obtained with our algorithm

Published in:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  (Volume:18 ,  Issue: 8 )