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Preparation of silicon-on-gallium arsenide wafers for monolithic optoelectronic integration

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4 Author(s)
London, Joanna M. ; Microsystems Technol. Lab., MIT, Cambridge, MA, USA ; Loomis, A.H. ; Ahadian, J.F. ; Fonstad, C., Jr.

A process is described which combines silicon-on-insulator (SOI) and wafer bonding techniques to create thin (/spl ap/100 nm) single-crystal silicon layers on oxide coated gallium arsenide wafers for use in optoelectronic integration. Using a GaAs substrate for the integration eliminates the thermal expansion coefficient mismatch problems which have blocked monolithic integration of thick, stress sensitive optoelectronic devices on silicon, without compromising the performance of CMOS circuitry which can be fabricated in very thin, compressively strained silicon layers using SOT techniques.

Published in:

Photonics Technology Letters, IEEE  (Volume:11 ,  Issue: 8 )