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The incredible shrinking transistor

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1 Author(s)
Yuan Taur ; IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA

The steady down-scaling of CMOS device dimensions has been the main stimulus to the growth of microelectronics and the computer industry over the past two decades. The more an IC is scaled, the higher becomes its packing density, the higher its circuit speed, and the lower its power dissipation. Today, after many generations of scaling, the smallest feature in a CMOS transistor is approaching atomic dimensions and off-state leakage current per transistor has been rising because thermal energy does not scale. So how much longer can CMOS scaling continue? As the integration level of ICs moves toward 100 million transistors in the next few years, key issues of transistor design must be reexamined for 0.10-0.13-μm generation technology. In previous CMOS generations, it was possible to disregard many parasitic components like off-state leakage and gate current. But in the not-so-distant future, these undesirables will grow rapidly as the fundamental limits imposed by thermodynamics and quantum mechanics close in on the technology. Fortunately the margins in today's devices will be enough to blunt the impact of such effects for perhaps a few generations. All the same, extracting the most performance while extending the limit of CMOS will require several elaborate schemes, including multiple threshold voltages, optimum two-dimensional nonuniform doping, and near atomic level control of gate oxide thickness and source-drain profile

Published in:

Spectrum, IEEE  (Volume:36 ,  Issue: 7 )

Date of Publication:

Jul 1999

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