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A development system for creating real-time machine vision hardware using field programmable gate arrays

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4 Author(s)
Drayer, T.H. ; Bradley Dept. of Electr. Eng., Virginia Polytech. Inst. & State Univ., Blacksburg, VA, USA ; Tront, J.G. ; Conners, R.W. ; Araman, P.A.

In this paper, we introduce a new development system for creating real-time image processing hardware using custom computing machines with multiple Field Programmable Gate Array (FPGA) chips. Three distinct processes are accomplished within the development system: design entry, verification, and translation. A library of modules that implement common low-level machine vision functions is used to create complex designs based on a dataflow graph representation. The library's low-level image processing modules contain both gate-level and chip-level hardware components, of which the gate-level components are compiled into the functionality of available FPGA chips. Standard interfaces are established for input/output of the modules, allowing for the creation of sophisticated software support tools. Experimental results verify the utility of this development system for easily creating real-time machine vision hardware using multiple FPGA-based custom computing machines.

Published in:

Systems Sciences, 1999. HICSS-32. Proceedings of the 32nd Annual Hawaii International Conference on  (Volume:Track3 )

Date of Conference:

5-8 Jan. 1999

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