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MOS capacitance measurements for high-leakage thin dielectrics

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2 Author(s)
Yang, K.J. ; Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA ; Chenming Hu

As oxide thickness is reduced below 2.5 nm in MOS devices, both series and shunt parasitic resistances become significant in capacitance-voltage (C-V) measurements. A new technique is presented which allows the frequency-independent device capacitance to be accurately extracted from impedance measurements at two frequencies. This technique is demonstrated for a 1.7 nm SiO2 capacitor

Published in:

Electron Devices, IEEE Transactions on  (Volume:46 ,  Issue: 7 )