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A 2000-MOPS embedded RISC processor with a Rambus DRAM controller

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12 Author(s)
Suzuki, K. ; Syst. ULSI Res. Lab., NEC Corp., Sagamihara, Japan ; Daito, M. ; Inoue, T. ; Nadehara, K.
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We have developed a 0.25-μm, 200-MHz embedded RISC processor for multimedia applications. This processor has a dual-issue superscalar datapath that consists of a 32-bit integer unit and a 64-bit single-instruction multiple-data (SIMD) function unit that together have a total of five multiply-adders. An on-chip concurrent Rambus DRAM (C-RDRAM) controller uses interleaved transactions to increase the memory bandwidth of the Rambus channel to 533 Mb/s. The controller also reduces latency by using the transaction interleaving and instruction prefetching. A 64-bit, 200-MHz internal bus transfers data among the CPU core, the C-RDRAM, and the peripherals. These high-data-rate channels improve CPU performance because they eliminate a bottleneck in the data supply. The datapath part of this chip was designed using a functional macrocell library that included placement information for leaf cells and resulted in the SIMD function unit of this chip's having 68000 transistors per square millimeter

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:34 ,  Issue: 7 )

Date of Publication:

Jul 1999

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