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A real-time digital VCR encode/decode and MPEG-2 decode LSI implemented on a dual-issue RISC processor

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9 Author(s)
Mohri, A. ; Inf. Technol. R&D Center, Mitsubishi Electr. Corp., Kanagawa, Japan ; Yamada, A. ; Yoshida, T. ; Sato, H.
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A real-time system large-scale-integrated circuit (LSI) for digital video cassette recorder (DVCR) encoding/decoding and MPEG-2 decoding is implemented on a dual-issue RISC processor (DRISC) with dedicated hardware optimized for video-block processing. The DRISC achieves 972-MOPS software performance and can execute fixed-length data processing at the block level as well as processing at the macro-block level and above for the DVCR/MPEG-2. The dedicated hardware for variable-length coding/decoding can encode and decode codes for both the DVCR and the MPEG-2 by changing translation tables. The dedicated hardware for video-block loading can process video-block data transfers with half-pel operations. The LSI size is 7.7×7.2 mm2 in a 0.25-μm CMOS process

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Solid-State Circuits, IEEE Journal of  (Volume:34 ,  Issue: 7 )