By Topic

Phase accumulator synthesis algorithm for DDS applications

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $31
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Romero-Troncoso, R.de J. ; Guanajuato Univ., Puebla, Mexico ; Espinosa-Flores-Verdad, G.

An algorithm for area-speed optimisation in phase accumulator synthesis is presented. Digital direct synthesis (DDS) requires an efficient phase accumulator as its main functional block. However, fast phase accumulators are very area-demanding and the tradeoff between area and speed is very critical. The approach can be used for the optimisation and synthesis of phase accumulators in FPGAs and ASICs

Published in:

Electronics Letters  (Volume:35 ,  Issue: 10 )