By Topic

A fast nonenumerative automatic test pattern generator for path delay faults

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Tragoudas, S. ; Dept. of Electr. & Comput. Eng., Arizona Univ., Tucson, AZ, USA ; Karayiannis, D.

This paper presents a nonenumerative automatic test pattern generator for robustly testable path delay faults. In contrast to earlier work by I. Pomeranz, et al. (see IEEE Trans. Computer-Aided Design, vol. 14, p. 1505-15, Dec. 1995), the pattern generator takes into consideration the conditions for robust propagation while sensitizing sets of paths. This increases the probability of testing them robustly with a single test. Novel algorithms are described which identify sets that contain many such potentially compatible paths. The number of detected faults is estimated using a simple and fast method. The approach compares favorably to that of Pomeranz et al. in both fault detection and time performance

Published in:

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on  (Volume:18 ,  Issue: 7 )