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Synthesis of delay fault testable combinational logic

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4 Author(s)
Roy, K. ; Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA ; Abraham, J.A. ; De, K. ; Lusky, S.

The synthesis of combinational logic which is robust delay fault testable is developed. In a circuit, any reconvergent fanout may result in the presence of blocked paths and/or paths which can be sensitized only if some other path is also sensitized. Implicit don't care terms are used to detect these problems and a local transformation at the reconvergence point is used to upgrade the delay fault testability of the circuit. The sharing of terms in a multilevel circuit is preserved to the greatest extent possible. Good results have been obtained based on an implementation of the algorithm in the LISP programming language on a TI Explorer machine.<>

Published in:

Computer-Aided Design, 1989. ICCAD-89. Digest of Technical Papers., 1989 IEEE International Conference on

Date of Conference:

5-9 Nov. 1989