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High throughput VLSI implementation of discrete orthogonal transforms using bit-level vector-matrix multiplier

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2 Author(s)
Nayak, S.S. ; Dept. of Phys., SKCG Coll., Paralakhemundi, India ; Meher, P.K.

In this paper, we propose a fully pipelined two-dimensional (2-D) bit level systolic architecture for efficient implementation of discrete orthogonal transforms using a serial-parallel vector-matrix multiplication scheme based on the Baugh-Wooley algorithm. Apart from its regularity and simplicity, the proposed structure yields high throughput due to massive parallelism across the 2-D mesh. The area- and time-complexities of the proposed structure are (ON2) and O(2nN2), respectively, for implementation of N-point transform, where n is the wordlength

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Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on  (Volume:46 ,  Issue: 5 )