High throughput VLSI implementation of discrete orthogonal transforms using bit-level vector-matrix multiplier

In this paper, we propose a fully pipelined two-dimensional (2-D) bit level systolic architecture for efficient implementation of discrete orthogonal transforms using a serial-parallel vector-matrix multiplication scheme based on the Baugh-Wooley algorithm. Apart from its regularity and simplicity, the proposed structure yields high throughput due to massive parallelism across the 2-D mesh. The area- and time-complexities of the proposed structure are (ON²) and O(2nN²), respectively, for implementation of N-point transform, where n is the wordlength