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Test generation for linear time-invariant analog circuits

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2 Author(s)
Chen-Yang Pan ; Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA ; Kwang-Ting Cheng

In this paper, we propose a cost-effective test generation technique for linear time-invariant analog circuits subject to the parametric faults. This technique requires only a small number of test patterns, as opposed to traditional functional testing which utilizes complex stimuli, to classify the circuits. We formulate the test-generation problem as a problem of deriving hyperplanes in the multidimensional space formed by a set of parameters of the device under test (DUT). These hyperplanes define the acceptance region in the measurement space and can be derived by a search-based heuristic. The coefficients of the hyperplanes are then used as test patterns for classification (to determine whether the DUT is in the acceptance region or not). A more general case of using arbitrary “linearly independent” test sequence for classification is also discussed. Experimental results show that less than 10% of misclassification can be achieved by a very small number of tests

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IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing  (Volume:46 ,  Issue: 5 )