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Analog circuit performance and process scaling

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1 Author(s)
A. -J. Annema ; Philips Res. Lab., Eindhoven, Netherlands

With newer CMOS processes, minimum transistor dimensions decrease and the supply voltage steadily gets lower. This trend is driven by the performance of digital systems: their level of performance (speed) increases while at the same time the cost (power consumption and die area) decreases. However, the performance of analog or mixed-signal circuits in newer CMOS generations does not necessarily improve. In this paper, trends in CMOS technology and supply voltage in relation to the performance of analog blocks in mixed-signal chips are analyzed. First, a relation for the absolute minimum power consumption of analog circuits is derived, based on a specific signal-to-noise and-distortion ratio (SINAD) over the full signal bandwidth. This limit shows that power consumption increases considerably with decreasing supply voltage, even at a constant performance level. The second part of this paper illustrates the trend in power consumption for actual analog circuits with SINAD demands. A quasi-differential CMOS voltage-follower circuit is used as a demonstration vehicle. In newer CMOS processes, the MOS transistors in the circuit get better, which tends to decrease the power consumption. The combined effect of the improving MOS transistors and the decreasing supply voltage is that power consumption at constant performance decreases down to about the 0.25-0.35-μm CMOS generations, and increases with newer CMOS generations thereafter. Ultimately, low supply voltages limit circuit feasibility or performance feasibility of analog circuits in newer CMOS processes

Published in:

IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing  (Volume:46 ,  Issue: 6 )