Cart (Loading....) | Create Account
Close category search window

Simple low power analogue MOS voltage adder

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $31
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Al-Nsour, M. ; Dept. of Electr. & Syst. Eng., Oakland Univ., Rochester, MI, USA ; Abdel-Aty-Zohdy, H.S.

A simple, low power, NMOS analogue voltage adder, suitable for VLSI implementation is presented. It is based on the inherent square law of MOS transistors operating in saturation mode. Using a 3.3 V source, the circuit's input voltage range is ±3 V, with an error less than 0.3% compared with the ideal sum of the inputs. The power consumption is <0.5 mW and THD <-36 dB for the full range of operation

Published in:

Electronics Letters  (Volume:35 ,  Issue: 7 )

Date of Publication:

1 Apr 1999

Need Help?

IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2014 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.