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Simple low power analogue MOS voltage adder

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2 Author(s)
Al-Nsour, M. ; Dept. of Electr. & Syst. Eng., Oakland Univ., Rochester, MI, USA ; Abdel-Aty-Zohdy, H.S.

A simple, low power, NMOS analogue voltage adder, suitable for VLSI implementation is presented. It is based on the inherent square law of MOS transistors operating in saturation mode. Using a 3.3 V source, the circuit's input voltage range is ±3 V, with an error less than 0.3% compared with the ideal sum of the inputs. The power consumption is <0.5 mW and THD <-36 dB for the full range of operation

Published in:

Electronics Letters  (Volume:35 ,  Issue: 7 )

Date of Publication:

1 Apr 1999

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