Cart (Loading....) | Create Account
Close category search window
 

Hybrid carry-select statistical carry look-ahead adder

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $31
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Corsonello, P. ; Dept. of Electron. Eng. & Appl. Math., Calabria Univ., Italy ; Perri, S. ; Cocorullo, G.

A new high-performance variable time adder is presented which is based on the statistical carry look-ahead addition technique. The new circuit uses carry-select stages to reduce the critical path. A 56 bit adder designed for and realised using 0.5 μm CMOS technology shows an average addition time of ~1.28 ns

Published in:

Electronics Letters  (Volume:35 ,  Issue: 7 )

Date of Publication:

1 Apr 1999

Need Help?


IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2014 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.