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Hybrid carry-select statistical carry look-ahead adder

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3 Author(s)
Corsonello, P. ; Dept. of Electron. Eng. & Appl. Math., Calabria Univ., Italy ; Perri, S. ; Cocorullo, G.

A new high-performance variable time adder is presented which is based on the statistical carry look-ahead addition technique. The new circuit uses carry-select stages to reduce the critical path. A 56 bit adder designed for and realised using 0.5 μm CMOS technology shows an average addition time of ~1.28 ns

Published in:

Electronics Letters  (Volume:35 ,  Issue: 7 )

Date of Publication:

1 Apr 1999

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