By Topic

Walk-time address adjustment for improving the accuracy of dynamic branch prediction

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Chien-Ming Chen ; Dept. of Comput. Sci., Nat. Tsing Hua Univ., Hsinchu, Taiwan ; Chung-Ta King

Dynamic branch prediction has been an effective technique for boosting the performance of modern high performance microprocessors. Since hardware predictors only have a limited number of 2-bit counters but programs often have a large, variable number of branches, two branches in the programs may thus be mapped to the same 2-bit counter. Predictions for these two branches may interfere with each other. This, in turn, reduces the prediction accuracy. In this paper, we discuss how a pre-run-time optimization technique, called address adjustment, can help to reduce branch interference. The technique adjusts the addresses of conditional branches in the given program by inserting NOP instructions at appropriate locations. In this way, the mapping between the conditional branches and the 2-bit counters can be controlled and branch interference can be minimized. Address adjustment can be applied at compile or link time, and the latter makes it a walk-time transformation technique. Three possible address adjustment schemes are investigated: constrained address adjustment, relaxed address adjustment, and branch classification. Experimental results show that address adjustment can reduce branch misprediction ratios on existing hardware predictors. Among the three methods, branch classification has the most improvement

Published in:

Computers, IEEE Transactions on  (Volume:48 ,  Issue: 5 )