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Mixed-mode simulation of compiled VHDL programs

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3 Author(s)
Acosta, R.D. ; Microelectron. & Comput. Technol. Corp., Austin, TX, USA ; Smith, S.P. ; Larson, J.

The VHSIC hardware description language (VHDL) supports the hierarchical design, documentation, and simulation of a wide range of digital system abstractions. VHDL, however, is often cited as difficult to use and inefficient for simulating designs below the gate level. The authors present the mixed-mode simulation facilities of a VHDL system that overcome this limitation by effectively merging gate and switch primitive evaluation routines with VHDL processes. A high-performance mixed-mode simulation capability is achieved through integrated approaches to interface compilation, data structuring, and implementation of the simulation cycle. Several experimental results serve as preliminary justification for this methodology.<>

Published in:

Computer-Aided Design, 1989. ICCAD-89. Digest of Technical Papers., 1989 IEEE International Conference on

Date of Conference:

5-9 Nov. 1989

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