By Topic

High performance test generation for accurate defect models in CMOS gate array technology

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
H. Sucar ; CrossCheck Technol. Inc., San Jose, CA, USA ; S. J. Chandra ; D. J. Wharton

A brief description is given of the CrossCheck test technology which provides the fundamental basis for this work. The authors present a practical analysis of transistor-level defects which result in accurate defect models in comparison to conventional fault models. The embedded test technology and accurate defect models are combined to form a high-quality test environment which is used to implement a high-performance test generation system. The authors present results on five ISCAS sequential benchmark circuits and two real designs. These results indicate that, in the presence of the embedded test electronics, test generation and fault simulation are considerably faster and test quality is substantially improved.<>

Published in:

Computer-Aided Design, 1989. ICCAD-89. Digest of Technical Papers., 1989 IEEE International Conference on

Date of Conference:

5-9 Nov. 1989