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An accurate timing model for fault simulation in MOS circuits

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2 Author(s)
Kim, S. ; Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA ; Banerjee, P.

An accurate timing model is presented for MOS circuits, which is based on a multiple-valued logic representation, accurate RC models for delay calculations derived from transistor characteristics and slope information, and accurate models for physical failures. A delay fault simulator (FACT) based on this model has been implemented. Results for various MOS circuits are described and compared with those for SPICE and RSIM.<>

Published in:

Computer-Aided Design, 1989. ICCAD-89. Digest of Technical Papers., 1989 IEEE International Conference on

Date of Conference:

5-9 Nov. 1989