Referenced Items are not available for this document.
An accurate timing model is presented for MOS circuits, which is based on a multiple-valued logic representation, accurate RC models for delay calculations derived from transistor characteristics and slope information, and accurate models for physical failures. A delay fault simulator (FACT) based on this model has been implemented. Results for various MOS circuits are described and compared with those for SPICE and RSIM.<
Published in:
Computer-Aided Design, 1989. ICCAD-89. Digest of Technical Papers., 1989 IEEE International Conference on
Date of Conference: 5-9 Nov. 1989
- Page(s):
- 76 - 79
- Meeting Date :
- 05 Nov 1989-09 Nov 1989
- Print ISBN:
- 0-8186-1986-4
- INSPEC Accession Number:
- 3695622
- Conference Location :
- Santa Clara, CA, USA
- Digital Object Identifier :
- 10.1109/ICCAD.1989.76908
- Product Type:
- Conference Publications
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