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Module assignment and interconnect sharing in register-transfer synthesis of pipelined data paths

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2 Author(s)
N. Park ; Dept. of Electr. & Comput. Eng., California Univ., Irvine, CA, USA ; F. J. Kurdahi

The authors present a novel approach to the problem of register-transfer (RT) design optimization of pipelined data paths. They perform module assignment with the goal of maximizing the interconnect sharing between RT-level components. The interconnect sharing task is modeled as a constrained clique partitioning problem. They have developed a fast and efficient polynomial time heuristic procedure to solve this problem. This procedure is 30-50 times faster than other existing heuristics while still producing better results for the authors' purposes.<>

Published in:

Computer-Aided Design, 1989. ICCAD-89. Digest of Technical Papers., 1989 IEEE International Conference on

Date of Conference:

5-9 Nov. 1989