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Transistors used for cellular and PCS infrastructure applications are required to amplify signals with a peak-average ratio that can exceed 13 dB, resulting in a PEP approaching 1 kW. This PEP requirement is a consequence of simultaneous amplification of multiple digitally modulated carriers with a time-varying envelope, and requires a load resistance in the neighborhood of 0.3 /spl Omega/. Present load-pull technology, based on mechanical tuners, is limited to approximately 1 /spl Omega/ at cellular and PCS frequencies, which render these systems incapable of characterizing transistors under these conditions. Previously, many researchers have developed quarter-wave pre-matching networks to transform the source- and load-pull domains to a lower impedance. To characterize these quarter-wave networks, a variety of techniques have been used, including analytical characterization, full-wave characterization, and standard VNA error correction characterization. This paper presents a further refinement of the third approach, which is based on a two-tier calibration using 7 mm and micro-strip TRL calibrations. The accuracy of each tier is quantified by employing offset-short and delay standards to extract the source- and load-match error response. It is shown that from 0.85 GHz to 3.0 GHz forward and reverse source- and load-match are better than -45 dB and -52 dB, respectively. In conjunction with a Maury automated load-pull system, using MT981B tuners, an impedance of 0.10 /spl Omega/ at 1900 MHz is developed.