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CMOS distributed amplifier design using CAD optimization techniques

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3 Author(s)
Allstot, D.J. ; Dept. of Electr. Eng., Arizona State Univ., Tempe, AZ, USA ; Ballweber, B.M. ; Gupta, R.

A four-stage distributed amplifier exhibits 6.5 dB gain, 5.5 GHz bandwidth, and 80 mW power dissipation from a 3 V supply in 0.6 μm CMOS. Scalable inductor models and custom CAD tools optimize performance

Published in:

Mixed-Signal Design, 1999. SSMSD '99. 1999 Southwest Symposium on

Date of Conference:

1999