A concurrent substrate coupling noise modeling technique for mixed-signal physical design

In this paper, a new mixed-signal substrate coupling noise analysis technique is presented. This analysis technique combines the simplicity of a parasitic circuit model with computational feasibility for concurrent simulation. It can compute substrate coupling noise from multiple digital noise sources. A hierarchical approach is adapted to model substrate coupling noise in three steps. The substrate itself is modeled as a 3D resistor mesh and lumped parasitic circuits of devices are extracted from the layout. The real-time waveform from logic simulation is imposed on each of the lumped parasitic circuit units. The SPICE netlist is generated accordingly throughout the modeling steps. The simulation results are presented and compared with results from MOSIS 1.2 /spl mu/m CMOS test chips. The accuracy issues of the modeling techniques are also discussed.