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Term rewriting systems (TRSs) offer a convenient way to describe parallel and asynchronous systems and prove an implementation's correctness with respect to a specification. TRS descriptions, augmented with proper information about the system building blocks, also hold the promise of high-level synthesis. High-level architectural descriptions that are both automatically synthesizable and verifiable would permit architectural exploration at a fraction of the time and cost required by current commercial tools. In this article, we use TRSs to describe a speculative processor capable of register renaming and out-of-order execution. We lack space to discuss a synthesis procedure from TRSs or to provide the details needed to make automatic synthesis feasible; Nevertheless, we show that our speculative processor produces the same set of behaviors as a simple nonpipelined implementation. Our descriptions of microarchitectures are more precise than those found in modern textbooks. The clarity of these descriptions lets us study the impact of features such as write buffers or caches, especially in multiprocessor systems.