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A multi-threading architecture for multilevel secure transaction processing

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3 Author(s)
Isa, H.R. ; United States Navy, Washington, DC, USA ; Shockley, W.R. ; Irvine, C.E.

A TCB and security kernel architecture for supporting multi-threaded, queue-driven transaction processing applications in a multilevel secure environment is presented. Our design exploits hardware security features of the Intel 80×86 processor family. Intel's CPU architecture provides hardware with two distinct descriptor tables. We use one of these in the usual way for process isolation. For each process, the descriptor table holds the descriptors of “system-low” segments, such as code segments, used by every thread in a process. We use the second table to hold descriptors for segments known to individual threads within the process. This allocation, together with an appropriately designed scheduling policy, permits us to avoid the full cost of process creation when only switching between threads of different security classes in the same process. Where large numbers of transactions are encountered on transaction queues, this approach has benefits over traditional multilevel systems

Published in:

Security and Privacy, 1999. Proceedings of the 1999 IEEE Symposium on

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