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Increase of parasitic resistance in shallow p+ extension by SiN sidewall process and its improvement by Ge preamorphization for sub-0.25-μm pMOSFET's

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6 Author(s)
S. Inaba ; R&D Center, Toshiba America Electron. Components Inc., Hopewell Junction, NY, USA ; A. Murakoshi ; M. Tanaka ; H. Yoshimura
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Anomalously high parasitic resistance is observed when SiN gate sidewall spacer is incorporated into sub-0.25-μm pMOSFET's. The parasitic resistance in p+ S/D extension region increases remarkably by decreasing BF2 ion implantation energy to lower than 10 keV. It is confirmed that low activation efficiency of boron in p+ extension is the reason for such high parasitic resistance. The reduction of activation efficiency of boron may result from hydrogen passivation of boron acceptor; Fourier transform infrared absorption (FT-IR) measurement suggests that diffused hydrogen from SIN into p+ extension region forms the silicon-hydrogen-boron complex. It is also found that the activation efficiency of boron correlates well both with implantation energy of BF2 and the amorphization rate of substrate. Therefore, in sub-0.25-μm era, the extra amorphization step is essential not only to form a shallow junction but also to enhance boron activation. Germanium preamorphization implantation (Ge PAI) is hence applied to p+ extension of 0.15 μm pMOSFET's. It is finally demonstrated that this Ge PAI process reduces the total parasitic resistance to improve the drain saturation current by up to 10%

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IEEE Transactions on Electron Devices  (Volume:46 ,  Issue: 6 )