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A pixel-parallel image processor using logic pitch-matched to dynamic memory

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2 Author(s)
Gealow, J.C. ; Dept. of Electr. Eng. & Comput. Sci., MIT, Cambridge, MA, USA ; Sodini, C.G.

A pixel-parallel image processor provides the capability for desktop systems to perform low-level image processing tasks in real time. Compact logic units are pitch-matched to DRAM columns to form dense blocks of processing elements. The processing elements are interconnected to form a 64×64 array, with each processing element assigned to a single pixel. Operating with a 60-ns clock cycle in a complete system, fully functional devices dissipate 300 mW. Using the devices, low-level image processing tasks have been performed in real time with input images provided at rates exceeding 30 frames/s

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Solid-State Circuits, IEEE Journal of  (Volume:34 ,  Issue: 6 )