By Topic

A 2.5-Gb/s clock and data recovery IC with tunable jitter characteristics for use in LANs and WANs

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Kishine, K. ; NTT Network Innovation Labs., Kanagawa, Japan ; Ishihara, N. ; Takiguchi, K. ; Ichino, H.

A 2.5-Gb/s monolithic clock and data recovery (CDR) IC using the phase-locked loop (PLL) technique is fabricated using Si bipolar technology. The output jitter characteristics of the CDR can be controlled by designing the loop-gain design and by using the switched-filter PLL technique. The CDR IC can be used in local-area networks (LANs) and in long-haul backbone networks or wide-area networks (WANs). Its power consumption is only 0.4 W. For LANs, the jitter generation of the CDR when the loop gain is optimized is 1.2 ps (0.003 UI). The jitter characteristics of the CDR optimized for WANs meet all three types of STM-I6 jitter specifications given in ITU-T Recommendation G.958. This is the first report on a CDR that can be used for both LAN's and WAN's. This paper also describes the design method of the jitter characteristics of the CDR for LANs and WANs

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:34 ,  Issue: 6 )