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Variable length coding is a widely used technique in digital video compression systems. Previous work related to variable length decoders (VLDs) was primarily aimed at high throughput applications, but the increased demand for portable multimedia systems has made power a very important factor. In this paper, a data-driven variable length decoding architecture is presented, which exploits the signal statistics of variable length codes to reduce power. The approach uses fine-grain lookup table (LUT) partitioning to reduce switched capacitance based on codeword frequency. The complete VLD for MPEG-2 has been fabricated and consumes 530 /spl mu/W at 1.35 V with a video rate of 48-M discrete cosine transform samples/s using a 0.6-/spl mu/m CMOS technology. More than an order of magnitude power reduction is demonstrated without performance loss compared to a conventional parallel decoding scheme with a single LUT.
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on (Volume:7 , Issue: 2 )
Date of Publication: June 1999