By Topic

A cost-effective design for testability: clock line control and test generation using selective clocking

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Sanghyeon Baeg ; Cisco Syst. Inc., San Jose, CA, USA ; Rogers, W.A.

Clock line control (CLC) is proposed as a new design for testability technique which can transform a complex test generation problem into many small ones that are efficiently manageable by selectively enabling or disabling the synchronous operation of modules. A novel sequential test generation technique for the circuits with CLC scheme is also presented. The new test generation methodology is able to selectively clock modules, expand multiple time frames for a sequential module and compose these local time frames to generate input and clock vectors for an entire circuit. Test generation for the ISCAS'89 circuits, with and without CLC has been performed. Higher fault coverage in a shorter time has been achieved using test generation with CLC

Published in:

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on  (Volume:18 ,  Issue: 6 )