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A new framework for automatic generation, insertion and verification of memory built-in self test units

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2 Author(s)
Zarrineh, K. ; IBM Corp., Endicott, NY, USA ; Upadhyaya, S.J.

The design and architecture of a memory test synthesis framework for automatic generation, insertion and verification of memory BIST units is presented. We use a building block architecture which results in full customization of memory BIST units. The flexibility and efficiency of the framework are demonstrated by showing that memory BIST units with different architecture and characteristics could be generated, functionally verified and inserted in a short time. Custom memory test algorithms could be loaded in the supported programmable BIST unit and therefore any type of memory test algorithm could be realized

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VLSI Test Symposium, 1999. Proceedings. 17th IEEE

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