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New procedures for identifying undetectable and redundant faults in synchronous sequential circuits

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4 Author(s)
Reddy, S.M. ; Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA ; Pomeranz, I. ; Xijiang Lin ; Basturkmen, N.Z.

We present three new procedures for identifying undetectable and redundant faults in synchronous sequential circuits. The procedures use an iterative logic array of limited length, into which faults are injected in different ways. The proposed procedures help identify undetectable and redundant faults that cannot be identified by existing procedures based on iterative logic arrays of limited length

Published in:

VLSI Test Symposium, 1999. Proceedings. 17th IEEE

Date of Conference:

1999