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A fault simulation based test pattern generator for synchronous sequential circuits

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3 Author(s)
Ruifeng Guo ; Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA ; Pomeranz, I. ; Reddy, S.M.

We describe a fault simulation based test generation procedure for synchronous sequential circuits. Several techniques are used to generate test sequences to achieve high fault coverages at low computational complexity. Experimental results presented demonstrate that the proposed procedure achieves fault coverages which are in all cases the same or higher than those achieved by existing procedures. The run times of the procedure are considerably smaller compared to the existing procedures

Published in:

VLSI Test Symposium, 1999. Proceedings. 17th IEEE

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