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Simulation-based design error diagnosis and correction in combinational digital circuits

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2 Author(s)
D. Nayak ; Cadence Design Syst., Chelmsford, MA, USA ; D. M. H. Walker

This paper describes an approach to design error diagnosis and correction in combinational digital circuits. Our approach targets small errors introduced during the design process or due to specification changes. We incrementally use simulation to identify suspect nets, and then attempt correction based on our error model. We use multiple iterations to handle multiple errors. Experimental results on ISCAS'85 benchmarks are shown for circuits containing up to four random errors. Diagnosis and correction can be done quickly, with the bulk of the time going to diagnosis. Our tool is accurate in that even with multiple errors present, the corrected circuit is identical to the original most of the time

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VLSI Test Symposium, 1999. Proceedings. 17th IEEE

Date of Conference: