By Topic

Performance analysis of single stage interconnection networks

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Burke, J.R. ; Semicond. Res. Corp., Research Triangle Park, NC, USA ; Chen, C. ; Lee, T.-Y. ; Agrawal, D.P.

A single-stage interconnection network (SSIN) consisting of only one stage of switches and recirculation through processors is studied. An analytical probability model for SSINs using 2×2 switches is introduced, and results obtained with the model are compared with simulation results. Four SSINs with different network sizes, loading, and routing strategies are discussed. Processors with and without buffers are considered, and three different routing strategies are applied to resolve conflicts. The analytical model is seen to be in close agreement with the simulation results while providing at least an order of magnitude reduction in CPU time

Published in:

Computers, IEEE Transactions on  (Volume:40 ,  Issue: 3 )