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Processing thick multilevel polyimide films for 3-D stacked memory

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5 Author(s)
Caterer, M.D. ; IBM Microelectron. Div., Essex Junction, VT, USA ; Daubenspeck, T.H. ; Ference, T.G. ; Holmes, S.J.
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This paper discusses thick polyimide film processing for a three-dimensional (3-D) semiconductor chip-stacking application. The formation of a complex, multilevel via structure is demonstrated. The issues that arise in forming these vias relate to apply, develop, profile modification, and integration. Apply issues include “outgassing” defects, edge-bead effects, as well as the planarity and leveling of both resist and polyimide over deep-via structures. Develop issues pertain to the implementation of a thick resist process that increases the structural integrity of the resist and controls its breakage, and to a vacuum bake before applying resist, which reduces solvent absorption into the resist. Profile modification issues include rounding via edges while minimizing bulk polyimide loss and maintaining image-size control. Developer attack of the metal pads during wet processing is discussed and a solution is proposed. Finally, additional process-integration issues relating to polyimide-to-metal adhesion and composite stress levels of the multilayer thick films are presented

Published in:

Advanced Packaging, IEEE Transactions on  (Volume:22 ,  Issue: 2 )