By Topic

The use of a WLR technique to characterize voiding in 0.25 and 0.18 μm technologies for integrated circuits

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

7 Author(s)
Marathe, A. ; Technol. Dev. Group, Adv. Micro Devices Inc., Sunnyvale, CA, USA ; Besser, P. ; Tsiang, J. ; Tran, K.
more authors

A quantitative correlation has been successfully demonstrated between the isothermal wafer level test results and severity of voiding in sub-micron interconnect lines. Isothermal test T50% and T 0.1% decrease while sigma increases, as the voiding becomes more severe. The isothermal wafer level test gives a good signal to indicate a significant decrease in severity of voiding with an anneal after metal etch and when a TiN underlayer is present in the metal stack. The isothermal test is thus shown to be a useful reliability tool for process monitoring and void detection in VLSI interconnects

Published in:

Reliability Physics Symposium Proceedings, 1999. 37th Annual. 1999 IEEE International

Date of Conference: