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RAPPID: an asynchronous instruction length decoder

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10 Author(s)
Rotem, S. ; Strategic CAD Lab., Intel Corp., Hillsboro, OR, USA ; Stevens, K. ; Ginosar, R. ; Beerel, P.
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This paper describes an investigation of potential advantages and risks of applying an aggressive asynchronous design methodology to Intel Architecture. RAPPID (“Revolving Asynchronous Pentium(R) Processor Instruction Decoder”), a prototype IA32 instruction length decoding and steering unit, was implemented using self-timed techniques. RAPPID chip was fabricated on a 0.25 μ CMOS process and tested successfully. Results show significant advantages-in particular, performance of 2.5-4.5 instructions/nS-with manageable risks using this design technology. RAPPID achieves three times the throughput and half the latency, dissipating only half the power and requiring about the same area as an existing 400 MHz clocked circuit

Published in:

Advanced Research in Asynchronous Circuits and Systems, 1999. Proceedings., Fifth International Symposium on

Date of Conference:

1999

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