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AMULET3 revealed

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3 Author(s)
Garside, J.D. ; Dept. of Comput. Sci., Manchester Univ., UK ; Furber, S.B. ; Chung, S.-H.

AMULET3 is the third fully asynchronous implementation of the ARM architecture designed at the University of Manchester. It implements the most recent version of the ARM architecture (v4T), including the Thumb instruction set. Significant architectural changes from its predecessors help achieve higher performance without sacrificing the advantages of asynchronous design and some new power-saving features have been incorporated. This paper outlines the AMULET3 microprocessor core, highlighting where this design differs from its predecessors. Most notable among the changes are the use of a Harvard architecture to increase memory bandwidth and the inclusion of a recorder buffer to handle data forwarding and memory faults

Published in:

Advanced Research in Asynchronous Circuits and Systems, 1999. Proceedings., Fifth International Symposium on

Date of Conference:

1999

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