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Full scan fault coverage with partial scan

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3 Author(s)
Xijiang Lin ; Mentor Graphics Corp., Wilsonville, OR, USA ; Pomeranz, I. ; Reddy, S.M.

In this paper, a test generation based partial scan selection procedure is proposed. The procedure is able to achieve the same level of fault coverage as in a full scan design by scanning only a subset of the flip-flops. New measures are used to guide the flip-flop selection during the procedure. The proposed procedure is applied to the ISCAS-89 and the ADDENDUM-93 benchmark circuits. For all the circuits, it is possible to achieve the same fault coverage as that for full scan while scanning a portion of the flip-flops.

Published in:

Design, Automation and Test in Europe Conference and Exhibition 1999. Proceedings

Date of Conference:

9-12 March 1999