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A retargetable, ultra-fast instruction set simulator

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2 Author(s)
Jianwen Zhu ; Dept. of Inf. & Comput. Sci., California Univ., Irvine, CA, USA ; Gajski, D.D.

In this paper we present new techniques which further improve the static compiled instruction set architecture (ISA) simulation by the aggressive utilization of the host machine resources. Such utilization is achieved by defining a low level code generation interface specialized for ISA simulation, rather than the traditional approaches which use C as a code generation interface. We are able to perform the simulation at a speed up to 102 millions of simulated instructions per second (MIPS). This result is only 1.1-2.5 times slower than the native execution on the host machine, the fastest to the best of our knowledge. Furthermore, the code generation interface is organized to implement a RISC like virtual machine, which makes our tool easily retargetable to many host platforms

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Design, Automation and Test in Europe Conference and Exhibition 1999. Proceedings

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