By Topic

Fast, robust DC and transient fault simulation for nonlinear analogue circuits

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Z. R. Yang ; Dept. of Electron. & Comput. Sci., Southampton Univ., UK ; M. Zwolinski

The evaluation of analogue and mixed-signal test strategies and design for test techniques requires the fault simulation of analogue circuits. The need to reduce fault simulation time for has resulted in the research into concurrent analogue fault simulation, analogous to digital fault simulation. Concurrent simulation can reduce the simulation time by avoiding repeated construction of the circuit matrix. Fault collapsing and dropping is also desirable. A robust, fast algorithm for concurrent analogue fault simulation is presented in this paper. Three techniques for the automatic dropping of faults have been addressed: a robust closeness measurement technique; a late start rule and an early stop rule. The algorithm has been successfully applied to both DC and transient analyses. A significant increase in the speed of analogue fault simulation has been obtained

Published in:

Design, Automation and Test in Europe Conference and Exhibition 1999. Proceedings

Date of Conference: