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Temporal partitioning combined with design space exploration for latency minimization of run-time reconfigured designs

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2 Author(s)
M. Kaul ; Lab. for Digital Design Environ., Cincinnati Univ., OH, USA ; R. Vemuri

We present combined temporal partitioning and design space exploration techniques for synthesizing behavioral specifications for run-time reconfigurable processors. Design space exploration involves selecting a design point for each task from a set of design points for that task to achieve latency minimization of partitioned solutions. We present an iterative search procedure that uses a core ILP (integer linear programming) technique, to obtain constraint satisfying solutions. The search procedure explores different regions of the design space while accomplishing combined partitioning and design space exploration. A case study of the DCT (discrete cosine transform) demonstrates the effectiveness of our approach.

Published in:

Design, Automation and Test in Europe Conference and Exhibition 1999. Proceedings

Date of Conference:

9-12 March 1999