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The problem of checking the equivalence of combinational circuits is of key significance in the verification of digital circuits. Previously, several approaches have been proposed for solving this problem. Still, the hardness of the problem and the ever-growing complexity of logic circuits motivates studying and developing alternative solutions. In this paper we study the application of Boolean satisfiability (SAT) algorithms for solving the combinational equivalence checking (CEC) problem. Although existing SAT algorithms are in general ineffective for solving CEC, in this paper we show how to improve SAT algorithms by extending and applying recursive learning techniques to the analysis of instances of SAT. This in turn provides a new alternative and competitive approach for solving CEC. Preliminary experimental results indicate that the proposed improved SAT algorithm can be useful for a large variety of instances of CEC, in particular when compared with pure BDD-based approaches.
Date of Conference: 9-12 March 1999