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Enhancement of PMOS device performance with poly-SiGe gate

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4 Author(s)
Wen-Chin Lee ; Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA ; Watson, B. ; Tsu-Jae King ; Chenming Hu

Poly-Si and poly-Si/sub 0.75/Ge/sub 0.25/-gated PMOS transistors with a very thin gate oxide of 29 /spl Aring/ were fabricated. In addition to reduced gate-depletion effect (GDE) and reduced boron penetration, more favorable I/sub d/-V/sub d/ characteristics were observed for the poly-SiGe-gated transistors than poly-Si-gated transistors. This and the underlying superior hole mobility are explained with a universal mobility model based on V/sub g/, T/sub ox/, V/sub th/ and V/sub th/. Both reduced GDE and superior hole mobility contribute to the enhanced performance.

Published in:
Electron Device Letters, IEEE  (Volume:20 ,  Issue: 5 )

Date of Publication: May 1999

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