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Multiple layers of silicon-on-insulator islands fabrication by selective epitaxial growth

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4 Author(s)
Sangwoo Pae ; Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA ; Taichi Su ; Denton, J.P. ; Neudeck, G.W.

This paper presents for the first time, multiple layers of silicon-on-insulator (MLSOI) device islands fabricated using selective epitaxial growth (SEG) and epitaxial lateral overgrowth (ELO) techniques. MLSOI has the potential for ultra dense device integration. SOI device islands as small as 150 nm×150 nm, with thickness down to 40 nm have been fabricated. SOI device islands (5 μm×500 μm) in the second layer have shown no stacking faults in the 1290 islands inspected. To demonstrate the device quality material, fully depleted SOI (FD-SOI) P-MOSFET's were fabricated in the first layer SOI islands with gate lengths down to less than 170 nm. Typically they had low subthreshold leakage, below 0.2 pA/μm, and a subthreshold swing of 76 mV/dec was measured.

Published in:

Electron Device Letters, IEEE  (Volume:20 ,  Issue: 5 )